1. Field of the Invention
This invention relates to a multipurpose speed controllable processor for controlling various secondary storage devices for use in an information processing system.
2. Description of the Prior Art
In the past, I/O controllers have each been designed and constructed based on wired logic to have desired functions and processing efficiencies which comply with particular requirements. Accordingly, in the case of using an I/O device of a novel function and/or improved efficiency, it is necessary to design and construct a novel I/O controller for the exclusive use of such an I/O device which requires large development costs and many designers.
However, since the International Business Machines Corporation has adoped microprogram (MP) controlled logic in an I/O controller for the 2314 magnetic disk device in 1965, almost all I/O controllers have been shifted to the MP controlled logic.
As is known in the art, the I/O controller of the MP controlled logic has advantages such as (i) low cost, (ii) easy and accurate diagnosis, (iii) shortened design and debugging processes and (iv) high flexibility. When adding a new function, the I/O controller of the MP controlled logic type need not be reconstructed as much as the wired logic type I/O controller. Nevertheless, even in the MP controlled logic type, the new function cannot be added without any reconstruction.
Theoretically, various functional differences can be settled by the replacement of microprograms but no multipurpose speed controllable processor capable of such replacement has been put in practical use for the following reasons. Firstly, it is uneconomical that the I/O controller retains, as a multipurpose device, a variety of functions and speeds and secondly it is difficult to sharply shorten the read cycle time of a control memory (CM) for technical and economical reasons.
With the I/O controller of the microprogram controlled logic, however, by utilizing its high flexibility, which is the abovesaid advantage (iv), it is theoretically possible to provide a multipurpose speed controllable processor capable of performing a variety of functions.
A typical one of the conventional I/O controllers using the MP controlled logic (for example, IBM 2314 I/O controller, i.e., IBM 2844) performs the I/O control by changing and modifying its internal state, the I/O information, etc. stored in two register groups, under the control of MP instructions stored in the CM, and it is therefore possible to realize an I/O controller of different functions by rewriting the microprograms in the CM. Accordingly, if the device has a sufficient speed and sufficient control memory capacity, it can be used as a multipurpose speed controllable processor. However, this is very uneconomical, and hence is not preferred for practical use. The read cycle time of the CM (that is the sum of the read time of the element itself and the time spent in read circuits), which is technically and economically proper at present is about 100 ns at minimum. It is considered that substantial reduction of the read cycle time cannot be expected even in the future. On the other hand, on the side of the I/O controller, a magnetic drum controller having a transfer cycle of about 500 ns has been put in practical use even at present. In the case of the I/O controller of the MP controlled logic, since it is desirable to execute about ten steps of MP instructions during one transfer cycle, it is appreciably difficult even under existing circumstances to largely adopt the MP controlled logic in the magnetic drum controller. In view of this, future I/O controllers of higher speed will inevitably again adopt the wired logic instead of the MP controlled logic to comply with the requirement for higher speed. Also, with the conventional MP controlled logic, it is difficult to realize multipurpose speed controllable processor usable with future I/O controllers. Further, offsetting of various advantages of the MP controlled logic by use of the wired logic is a significant loss in practical use.
An I/O controller controlled using parallel MP operation is known, (for example, U.S. Pat. No. 3,654,617 issued Apr. 4, 1972). An speed controllable processor effecting dynamic allocation of the MP instruction cycle to a multiplex type I/O device and an speed controllable processor providing a long and a short word for reducing the control memory capacity are also known (for example, U.S. Pat. Nos. 3,766,524 issued Oct. 16, 1973 and 3,673,575 issued June 27, 1972, respectively). Further, a multipurpose I/O controller which raises the processing speed by simultaneously reading out two words is also known (for example, U.S. Pat. No. 3,753,236 issued Aug. 14, 1973). However, none of these satisfies simultaneously both the requirements of functions and speeds covering wide ranges for multipurpose speed controllable processor.